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White Electronic Designs
WV3EG264M64EFSU-D4
PRELIMINARY*
1GB - 2x64Mx64 DDR SDRAM UNBUFFERED
FEATURES
PC2700 @ CL2.5 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Auto and self refresh, (8K/64ms refresh) Serial presence detect Power supply: VCC/VCCQ: 2.5V 0.2V Dual Rank Standard 200 pin SO-DIMM package * Package height options: D4: 31.75 mm (1.25")
NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change without notice.
DESCRIPTION
The WV3EG264M64EFSU is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen 64Mx8 bit with 4 banks DDR SDRAMs in FBGA packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3
August 2005 Rev. 0
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PIN CONFIGURATION
PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SYMBOL PIN# VREF 51 VREF 52 53 VSS VSS 54 DQ0 55 DQ4 56 DQ1 57 DQ5 58 59 VCC VCC 60 DQS0 61 DM0 62 DQ2 63 DQ6 64 65 VSS VSS 66 DQ3 67 DQ7 68 DQ8 69 DQ12 70 VCC 71 72 VCC DQ9 73 DQ13 74 DQS1 75 DM1 76 VSS 77 78 VSS DQ10 79 DQ14 80 DQ11 81 DQ15 82 VCC 83 VCC 84 CK0 85 VCC 86 CK0# 87 VSS 88 VSS 89 VSS 90 DQ16 91 DQ20 92 DQ17 93 DQ21 94 95 VCC VCC 96 DQS2 97 DM2 98 DQ18 99 DQ22 100 SYMBOL PIN# VSS 101 VSS 102 DQ19 103 DQ23 104 DQ24 105 DQ28 106 VCC 107 VCC 108 DQ25 109 DQ29 110 DQS3 111 DM3 112 VSS 113 VSS 114 DQ26 115 DQ30 116 DQ27 117 DQ31 118 VCC 119 VCC 120 NC 121 NC 122 NC 123 NC 124 VSS 125 126 VSS NC 127 NC 128 NC 129 NC 130 VCC 131 VCC 132 NC 133 NC 134 NC 135 NC 136 VSS 137 VSS 138 NC 139 VSS 140 NC 141 VCC 142 VCC 143 VCC 144 CKE1 145 CKE0 146 NC 147 NC 148 A12 149 A11 150 SYMBOL PIN# A9 151 A8 152 VSS 153 VSS 154 A7 155 A6 156 A5 157 A4 158 A3 159 A2 160 A1 161 A0 162 VCC 163 VCC 164 A10 165 BA1 166 BA0 167 RAS# 168 WE# 169 CAS# 170 CS0# 171 CS1# 172 NC 173 NC 174 VSS 175 VSS 176 DQ32 177 DQ36 178 DQ33 179 DQ37 180 VCC 181 VCC 182 DQS4 183 DM4 184 DQ34 185 DQ38 186 VSS 187 VSS 188 DQ35 189 DQ39 190 DQ40 191 DQ44 192 VCC 193 VCC 194 DQ41 195 DQ45 196 DQS5 197 DM5 198 VSS 199 VSS 200 SYMBOL DQ42 DQ46 DQ43 DQ47 VCC VCC VCC CK1# VSS CK1 VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 NC NC
WV3EG264M64EFSU-D4
PRELIMINARY
PIN NAMES
A0-A12 BA0-BA1 DQ0-DQ63 DQS0-DQS7 CK0, CK0# CK1, CK1# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DM0-DM7 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 NC Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply (2.5V) Power Supply for DQS (2.5V) Ground Power Supply for Reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM No Connect
August 2005 Rev. 0
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WV3EG264M64EFSU-D4
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS1# CS0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S1# DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S1#
DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S0#
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S1#
DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S0#
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S1#
DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S0#
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S1#
DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S0#
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S1#
DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S0#
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S1#
DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S0#
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S1#
BA0-BA1 A0-A12 RAS# CAS# WE# CKE0 CKE1
DDR SDRAMs DDR SDRAMs DDR SDRAMs DDR SDRAMs DDR SDRAMs DDR SDRAMs DDR SDRAMs
Clock Wiring
Clock Input CK0/CK0# CK1/CK1# SDRAMs 8 SDRAMs 8 SDRAMs
VCCSPD VCC/VCCQ VREF VSS
SPD SCL DDR SDRAMs DDR SDRAMs DDR SDRAMs WP
SERIAL PD SDA A0 SA0 A1 SA1 A2 SA2
NOTE: All datalines are terminated through a 22 ohm series resistor
August 2005 Rev. 0
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Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Voltage on VCCQ supply relative to VSS Storage Temperature Operating Temperature Power Dissipation Short Circuit Current
WV3EG264M64EFSU-D4
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Symbol VIN, VOUT VCC VCCQ TSTG TA PD IOS Value -0.5 to 3.3 -1.0 to 3.6 -1.0 to 3.6 -55 to +150 0 to +70 16 50 Units V V V C C W mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
0C TA 70C, VCC = 2.5V 0.2V Symbol VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) Addr, CAS#, RAS#, WE# CS#, CKE CK, CK# DM Parameter Supply voltage DDR266/DDR333 (nominal VCC of 2.5V) I/O Supply voltage DDR266/DDR333 (nominal VCC of 2.5V) I/O Reference voltage I/O Termination voltage Input logic high voltage Input logic low voltage Input voltage level, CK and CK# Input differential voltage, CK and CK# Input crossing point voltage, CK and CK# Min 2.3 2.3 0.49*VCCQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 0.3 -32 -16 -16 -4 -10 -16.8 16.8 -9 9 Max 2.7 2.7 0.51*VCCQ VREF+0.04 VCCQ+0.30 VREF-0.15 VCCQ+0.30 VCCQ+0.60 VCCQ+0.60 32 16 16 4 10 -- -- -- -- Unit V V V V V V V V uA uA uA uA uA mA mA mA mA Note
1 2
3
Input leakage current
II
Output leakage current Output high current (normal strengh); VOUT = V +0.84V Output high current (normal strengh); VOUT = VTT -0.84V Output high current (half strengh); VOUT = VTT +0.45V Output high current (half strengh); VOUT = VTT -0.45V
IOZ IOH IOL IOH IOL
NOTES: 1. VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed 2% of the DC value 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
CAPACITANCE
VCC = 2.5V, VCCQ = 2.5V, TA = 25C, f = 1MHz Parameter Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#) Input Capacitance (CKE0, CKE1) Input Capacitance (CS0#, CS1#) Input Capacitance (CK0,CK0#, CK1, CK1#) Input Capacitance (DM0-DM7) Data and DQS input/output capacitance (DQ0-DQ63)
August 2005 Rev. 0
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT
Min 28 16 16 16 11 11
Max 44 24 24 24 13 13
Unit pF pF pF pF pF pF
4
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Parameter/Condition Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Differential Voltage, CK and CK# inputs Input Crossing Point Voltage, CK and CK# inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF +0.31 0.7 0.5*VCCQ-0.2
WV3EG264M64EFSU-D4
PRELIMINARY
AC OPERATING TEST CONDITIONS
Max VREF -0.31 VCCQ+0.6 0.5*VCCQ+0.2 Unit V V V V Note 1 1
NOTES: 1. VIH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
August 2005 Rev. 0
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WV3EG264M64EFSU-D4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0C TA 70C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V Parameter Symbol Conditions One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN); DQ, DM and DQS inputs change once per clock cycle; Address and control inputs change once every two clock cycles One device bank; Active-Read-Precharge; BL = 4; tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA; Address and control inputs change once per clock cycle All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE = LOW CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM One device bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address and other control inputs changing once per clock cycle Burst = 2; Reads; Continuous burst; One device bank active; Address and other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA Burst = 2; Writes; Continuous burst; One device bank active; Address and other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle tRC = tRFC(MIN) CKE < 0.2V Four device bank interleaving Reads Burst = 4 with auto precharge; tRC = tRFC(MIN); tCK = tCK(MIN); Address and control inputs change only during Active READ, or WRITE commands DDR333 @ CL = 2.5 Max 1080 Unit
Operating current
IDD0*
mA
Operating current Percharge powerdown standby current Idle standby current Active power-down standby current Active standby current Operating current
IDD1* IDD2P**
1320 80
mA mA
IDD2F**
720
mA
IDD3P**
560
mA
IDD3N**
800
mA
IDD4R*
1360
mA
Operating current Auto refresh current Self refresh current Orerating current
IDD4W* IDD5** IDD6** IDD7A*
1440 4640 80 3280
mA mA mA mA
NOTE: IDD specification is based on Micron components. Other DRAM Manufacturers specification may be different. * Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode. ** Value calculated as all module ranks in this operation condition.
August 2005 Rev. 0
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AC TIMING PARAMETERS
Parameter Row cycle time Refresh row cycle time Row active time RAS# to CAS# delay Row precharge time Row active to Row active delay Write recovery time Last data into Read command Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK# Output data access time from CK/CK# Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width Address and Control Input setup time (fast) Address and Control Input hold time (fast) Address and Control Input setup time (slow) Address and Control Input hold time (slow) Data-out high impedence time from CK/CK# Data-out low impedence time from CK/CK# Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tIS tIH tIS tIH tHZ tLZ
WV3EG264M64EFSU-D4
PRELIMINARY
335 Min 60 72 42 15 15 12 15 1 6 0.45 0.55 -0.6 -0.7 -- 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.75 0.75 0.7 0.7 -0.7 Max
Unit ns ns ns ns ns ns ns tCK ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns
70K
CL = 2.5
13 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25
+0.7
Note: AC Timing Parameters are based on Micron components. Other DRAM Manufacturers parameters may be different.
August 2005 Rev. 0
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WV3EG264M64EFSU-D4
PRELIMINARY
AC TIMING PARAMETERS (Continued)
Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Exit self refresh o non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Auto precharge write recovery + Precharge time Symbol tMRD tDS tDH tIPW tDIPW tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL 335 Min 10 0.4 0.4 2.2 1.75 75 200 tHP - tQHS tCL(min) or tCH(min) 0.4 15 (tWR/tCK) + (tRP/tCK) Max Unit ns ns ns ns ns ns tCK us ns ns ns tCK tCK
7.8 -- -- 0.55 0.6
August 2005 Rev. 0
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White Electronic Designs
WV3EG264M64EFSU-D4
PRELIMINARY
ORDERING INFORMATION FOR D4
Part Number WV3EG264M64EFSU335D4xG Speed 166MHz/333Mb/s CAS Latency 2.5 tRCD 3 tRP 3 Height* 31.75mm (1.25")
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D4
67.60 (2.661) 63.60 (2.504) Full R 2x 3.80 (0.150) MAX.
4.00 0.10 (0.158 0.039)
31.75 (1.25) 20 (0.787)
1 39 41 199
6.0 0.236
11.40 (0.449) 2.15 (0.085) 2.45 (0.098) 1.8 (0.071) 1.00 0.1 (0.04 0.0039) 4.20 (0.165) 2.40 (0.094)
47.40 (1.866)
2- 1.80 (0.071) 1.0 0.1 (0.04 0.0039) 0.60 (0.024) 0.45 0.03 (0.018 0.001) 0.25 (0.01) 2.55 Min (0.102 Min)
4.00 (0.158) MIN.
4.00 0.10 (0.158 0.039)
Tolerances: 0.15 (0.006) unless otherwise specified * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
August 2005 Rev. 0
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White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WV3EG264M64EFSU-D4
PRELIMINARY
PART NUMBERING GUIDE
WV 3 E G 264M 64 E F S U xxx D4 x G
WEDC MEMORY DDR GOLD DEPTH (Dual Rank) BUS WIDTH x8 FBGA 2.5V UNBUFFERED SPEED (MHz) PACKAGE 200 PIN COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT
August 2005 Rev. 0
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White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
1GB - 2x64Mx64 DDR SDRAM UNBUFFERED
WV3EG264M64EFSU-D4
PRELIMINARY
Revision History Rev #
Rev 0
History
Initial Release
Release Date
8-05
Status
Preliminary
August 2005 Rev. 0
11
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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